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M3488
256 x 256 DIGITAL SWITCHING MATRIX
.256 .BUI .NOEXTRAPI .EUROPEANTELEPHONESTANDARD .PCM .ACTUAL .TYPI .TYPI .5VP0WERSUPPLY .CMOS&TTLI .HI
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IO Ptot Tstg Top Supply Voltage Input Voltage Off State Output Voltage Current at Digital Outputs Total Package Power Dissipation Storage Temperature Range Operating Temperature Range
PREL IMINARY DATA
INPUT AND 256 OUTPUT CHANNEL CMOS DIGITAL SWITCHING MATRIX COMPATIBLE WITH M088 LDING BLOCK DESIGNED FOR LARGE CAPACITY ELECTRONIC EXCHANGES, SUBSYSTEMS AND PABX N NEEDED FOR NOT-BLOCKING SINGLE STAGE AND HIGHER CAPACITY SYNTHESIS BLOCKS (512 or 1024 channels) COMPATIBLE (32 serial channels per frame) INPUTS AND OUTPUTS MUTUALLY COMPATIBLE INPUT-OUTPUT CHANNEL CONNECTIONS STORED AND MODIFIED VIA AN ON CHIP 8-BIT PARALLEL MICROPROCESSOR INTERFACE CAL BIT RATE : 2Mbit/s CAL SYNCHRONIZATION RATE : 8KHz (time frame is 125s) NPUT/OUTPUT LEVELS COMPATIBLE GH DENSITY ADVANCED 1.2m HCMOS3 PROCESS
DIP40
PQFP44
ORDERING NUMBERS: M3488B1 M3488Q1
.CHANNELCONNECTI .OUTPUTCHANNELDI .I .TRANSFERTOTHEMI .TRANSFERTOTHEMI .TRANSFERTOTHEMI
Main instructions controlled by the microprocessor interface ON/DISCONNECTION SCONNECTION NSERTION OF A BYTE ON A PCM OUTPUT CHANNEL/DISCONNECTION CROPROCESSOR OF A SINGLE PCM OUTPUT CHANNEL SAMPLE CROPROCESSOR OF A SINGLE OUTPUT CHANNEL CONTROL WORD CROPROCESSOR OF A SELECTED 0 CHANNEL PCM INPUT DATA
Parameter
Test Conditions -0.3 to 7 -0.3 to VCC+0.3 -0.3 to VCC+0.3 30 1.5 -65 to 150 0 to 70
Unit V V V mA W C C
Stresses above those l isted under " Absolute Maximum Ratings" may cause permanent damage to the devi ce. This is a stress rati ngs only and functional operation of the device at these or any other conditions above those indicated in the operating conditions of this specificati on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect devi ce reliabili ty.
November 1994
1/18
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M3488
PIN CONNECTIONS (Top views)
OUT PCM0 OUT PCM1 OUT PCM2 OUT PCM3 OUT PCM4 OUT PCM5 OUT PCM6 OUT PCM7 35
N.C.
N.C.
44 CLOCK SYNC INP PCM7 INP PCM6 1 2 3 4 5 6 7 8 9 10 11 12 N.C.
43
42
41
40
39
38
37
36
34 33 32 31 30 29 N.C. WR CS1 CS2 RESET VSS C/D A1 S1 A2 S2
DIP40
INP PCM5 INP PCM4 INP PCM3 INP PCM2 INP PCM1 INP PCM0 V CC
PQFP44
RD 28 27 26 25 24 23 22 DR
13 D7
14 D6
15 D5
16 D4
17 N.C.
18 D3
19 D2
20 D1
21 D0
D93TL040A
EXCHANGE NETWORKS APPLICATIONS 256 PCM links network (160 or 192 DSM) : the 32 x 32 link module shown on the next page.
2048 PCM links network (1792 or 2048 DSM) : the 256 x 256 link network is shown above.
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M3488
EXCHANGE NETWORKS APPLICATIONS (continued) Single Stage/Sixteen Devices Configuration (32 by 32 links or 1024 channels).
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M3488
BLOCK DIAGRAM
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M3488
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vi VO CLOCK Freq. Top Supply Voltage Input Voltage Off State Input Voltage Input Clock Frequency Parameter Value 4.75 to 5.25 0 to 5.25 0 to 5.25 4.096 8 0 to 70 Unit V V V MHz KHz C
SYNC Freq. Input Synchronization Frequency Operating Temperature
CAPACITANCES (measurement freq. = 1MHz; Top = 0 to 70C; unused pins tied to VSS)
Symbol CI CI/O CO Parameter Input Capacitance I/O Capacitance Output Capacitance 20 to 24 1 to 4; 17 to 19; 25; 37 to 40 Pins (*) 6 to 15; 26 to 30; 32 to 36 Min. Typ. Max. 5 15 10 Unit pF pF pF
D.C. ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70C, VCC = 5V 5%) All D.C. characteristics are valid 250s after VCC and clock have been applied.
Symbol VILC VIHC VIL Parameter Clock Input Low Level Clock Input High Level Input Low Level Pins (*) 6 6 7 to 15 20 to 24 26 to 30 32 to 36 7 to 15 20 to 24 26 to 30 32 to 36 17 to 25 1 to 4 37 to 40 17 to 25 6 to 15 26 to 30 32 to 36 17 to 24 IOH = 5mA VOH = 2.4V IOL = 5mA VOL = 0.4V VIN = 0 to VCC 5 5 Test Condition Min. -0.3 2.4 -0.3 Typ. Max. 0.8 VCC 0.8 Unit V V V
VIH
Input High Level
2
VCC
V
VOH IOH VOL IOL IIL
Output High Voltage (Level) Output High Current Output Low Voltage (Level) Output Low Current Input Leakage Current
2.4 5 0.4
V mA V mA A
IDL
Data Bus Leakage Current
VIN = 0 to VCC VCC applied; Pins 35 and 36 tied to VCC, after Device Initialization Clock Freq. = 4.096MHz 15
5
A
ICC
Supply Current
16
30
mA
(*) T he pi n number i s referred to the DIP 40 ver sion.
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M3488
A.C. ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70C, VCC = 5V 5%) All A.C. characteristics are valid 250s after VCC and clock have been applied. CL is the max. capacitive load.
Signal CK (clock) Symbol tCK tWL tWH tR tF tSL tHL tSH tWH tS tH tPD min tPD max tSL tHL tSH tWH tWL tWH tREP tSH tHH tR tF Parameter Clock Period Clock Low Level Width Clock High Level Width Rise Time Fall Time Low Level Setup Time Low Level Hold Time High Level Setup Time High Level Width Setup Time Hold Time Propagation time referred to CK low level Propagation time referred to CK high level Low Level Setup Time Low Level Hold Time High Level Setup Time High level Width Low Lvel Width High Level Width Repetition Interval between Active Pulses High Level Setup Time to Active Read Strobe High Level Hold Time from Active Write Strobe Rise Time Fall Time C L = 150pF RL = 1K 60 30 80 tCK 100 tCK see formula 0 tREP 40 + 2 tCK + tWL(CK) + + tR(CK) 15 60 60 Test Condition Min. 230 100 100 Typ. 244 Max. Unit ns ns ns ns ns ns ns ns ns ns ns 110 110 140 ns ns ns ns ns ns ns ns ns ns ns ns ns
25 25 60 30 80 tCK 5 +40 45
SYNC (frame pulse)
PCM Input Busses PCM Output Busses Open Drain RESET
WR, RD
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M3488
A.C. ELECTRICAL CHARACTERISTICS (continued)
Signal CS1, CS2 Symbol tSL(CS-WR) tHL(CS-WR) tSH(CS-WR) tHH(CS-WR) tSL(CS-RD) tHL(CS-RD) tSH(CS-RD) tHH(CS-RD) C/D tS(C/D-WR) tH(C/D-WR) tS(C/D)-RD) tH(C/D-RD) A1, S1, A2, S2 (match inputs) tS(match-WR) tH(match-WR) tS(match-RD) tH(match-RD) DR (data ready) D0 to D7 (interface bus) tW tPD Parameter Low level setup time to WR falling edge Low Level hold time from WR rising edge High Level setup time to WR falling edge High level hold time from WR rising edge Low level setup time to RD falling edge Low level hold time from RD rising edge High level setup time RD falling edge High level hold time from RD Setup time to write strobe end Hold time from write strobe end Setup time to read strobe start Hold time from read strobe end Setup time to write strobe end Hold time from strobe end Setup time to read strobe start Hold time from read strobe end Low state width DR output delay from write strobe end (active command) Input setup time to write strobe end Input hold time from write strobe end Propagation time from (active) falling Edge of read strobe Propagation time from (active) rising Edge of read strobe to high impedance state Instructions 5 and 6 Instruction 5, CL = 150pF 4.tCK Test Condition Active Case Active Case Inactive Case Inactive Case Active Case Active Case Inactive Case Inactive Case Min. 0 0 0 0 0 0 0 0 Typ. Max. Unit ns ns ns ns ns ns ns ns
130 15 20 20 130 15 20 20 2.tCK 7.tCK
ns ns ns ns ns ns ns ns ns ns
tS(BUS-WR) tH(BUS-WR)
130 15
ns ns
tPD(BUS)
C L = 200pF
120
ns
tHZ(BUS)
C L = 200pF 80 ns
A.C. TESTING, OUTPUT WAVEFORM
A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0", timing measurement are made at 2.0V for a logic "1"and 0.8V for a logic "0". 7/18
M3488
PCM TIMING, RESET, SYNC
WRITE OPERATION TIMING
8/18
M3488
READ OPERATION TIMING
GENERAL DESCRIPTION The M3488 is intendedfor large telephoneswitching systems, mainly central exchanges, digital line concentrators and private branch exchanges where a distributed microcomputer control approach is extensively used. It consists of a speech memory (SM), a control memory (CM), a serial/parallel and a parallel/serial converter, an internal parallel bus, an interface (8 data lines, 11 control signals) and dedicated control logic. By means of repeated clock division two timebases are generated. These are preset from an external synchronization signal to two specific count numbers so that sequential scanning of the bases give synchronous addresses to the memories and I/O channel controls. Different preset count numbers are needed because of processing delays and data path direction. The timebase for the input channels is delayed and the timebase for output channels is advanced with respect to the actual time. Each serial PCM input channel is converted to parallel data and stored in the speech memory at the beginning of any new time slot (according to first timebase) in the location determined by input pin number and time slot number. The control memory CM maintains the correspondencesbetween input and output channels. More exactly, for any output pin/outputchannel combination the control memory gives either the full address of the speech memory location involved in the PCM transfer or an 8-bit word to be supplied to the parallel/serial output converter. A 9th bit at each CM location defines the data source for output links, low for SM, high for CM. The late timebase is used to scan the output channels and to determine the pins to be serviced within each channel ; enough idle cycles are left to the microprocessor for asynchronousinstruction processing. Two 8-bit registers OR1 and OR2 supply feedback data for control or diagnosticpurposes ; OR1 comes from internal bus i.e. from memories, OR2 gives an opcode copy and additional data to the microcomputer. A four byte-five bit stack register and an instruction register, under microcomputer control, store input data available at the interface. Dedicated logic, under controlof the microprocessor interface, extracts the 0 channel content of any selected PCM input bus, using spare cycles of SM.
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M3488
PINS FUNCTION
Pin Assignement Symbol Name DIP40 PQFP44
D7 to D0
Data bus
17 to 24
13 to 21
C/D
Input control
30 26 to 29 33, 34
27 23 to 26 30, 31
A1, S1, A2, S2 Address select or match CS1, CS2 Chip select
WR
Data transfer enable
35
32
RD DR RESET
Read enable Data ready RESET control
36 25 32
34 22 29
CLOCK
Input master clock
6
1
SYNC
Input synchronization
7 8 to 15 37 to 40 and 1 to 4
2 3 to 10 35 to 38 and 40 to 43
IN PCM 7 to 0 PCM input bus OUT PCM 7 to 0 PCM output bus
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M3488
PIN DESCRIPTION D7 to D0 Data bus pins. The bidirectional bus is usedto transfer dataand instructions to/fromthe microprocessor. D0 is the least significant digit. The output bus is 8 bits wide ; input is only 5 bits wide. (D4 to D0) The bus is tristate and cannot be used while RESET is held low. The meaning of input data, such as bus or channel numbers, and of expected output data is specified in detail by the instruction description. (Pagg. 12-14) C/D (pin 30) Input control pin, select pin. In a write operation C/D = 0 qualifies any bus content as data, while C/D = 1 qualifies it as an opcode. In a read operation OR1 is selected by C/D = 0, OR2 by C/D = 1. A1, S1, A2, S2 Address select or match pins. In a multi-chip configuration (e.g. a single stage matrix expansion), using the same CS pins, the match condition (A1 = S1 and A2 = S2) leaves the commandinstruction as defined; on the contrary the mismatch condition modifies the execution as follows : instructions 1 and 3 are reversed to channeldisconnection, instruction 5 is unaffected, instructions 2-4-6 are cancelled (not executed). Bus reading takes place only on match condition, instruction flow is in any case affected. Eachpins couple is commutative : in a multichip configuration pins S1 and S2 give a hard-wired address selection for individual matrixes, while in single configuration S1 and A1 or S2 and A2 are normally tied together. CS1, CS2 Commutative chip select pins. They enable the device to perform valid read/write operations (active low). Two pins allow row/column selection with different types of microprocessors ; normally one is tied to ground. WR Pin WR, when CS1 and CS2 are low, enables data transfer from microprocessor to the device. Data or opcode and controls are latchedon WR rising edge. Becauseof internal clock resynchronizationone single additionalrequirement is recommended in order to produce a simultaneous instruction execution in a multichip configuration: WR rising edge has to be 20 to 20 + tWL(CK) nsec late relative to clock falling edge. RD When CS1 andCS2 are low and match condition exists, a low level on RD enables a register OR1 or OR2 read operation, through the bidirectional bus. In addition, the rising edge of RD latches C/D and the match condition pins in order to direct the internal flow of operations. Because of internal clock resynchronization, one single additional requirement is recommended in order to produce a simultaneousinstruction flow in a multichip configuration: the RD rising edge has to be 20 to 20 + tWL(CK) nsec late relative to clock falling edge. DR Data ready. Normally high, DR output pin goes low to tell the microprocessor that : a) the instruction code was found to be invalid ; b) executing instruction 5 an active output channel was found in the whole matrix array, that is a CM word not all "ones" was found in a configuration of devices sharing the same CS pins ; c) executing instruction 6 "0 channel extraction" took place and OR2 was loaded with total number of messages inserted on 0 time slot. DR is active low about two clock cycles in case b and c ; in case a it is left low until a valid instruction code is supplied. RESET RESET control pin is normally used at the very beginning to initialize the device or the network. Any logical status is reset andCM is set to all "ones" after RESET going low. The internal initialization routine takes one time frame whatever the RESET width on low level (minimum one cycle roughly), but it is repeatedan integer number of time frames as long as RESET is found low during 0 time slot. Initialization pulls the interface bus immediately to a high impedance state. After the CM has been set to all "ones" the PCM output channels are also set to high impedance state. CLOCK Input master clock. Typical frequency is 4.096MHz. First division gives an internal clock controlling the input and output channels bit rate. SYNC Input synchronization signal is active low. Typical frequency is 8kHz.
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M3488
Internal time bases are forced by synchronism to an assigned count number in order to restore channels and bit sequential addressing to a known state. Count difference between the bases is 32, correspondingto two time slots, that is the minimum PCM propagation time, or latency time. INP PCM 7 to INP PCM 0 PCM input busses or pins ; they accept a standard 2Mbit/s rate. Bit 1 (sign bit) is the first of the serial sequence ; in a parallel conversion it is left adjusted as the most significant digit. OUT PCM 7 to OUT PCM 0 PCM output busses or pins ; bit rate and organization are the same as input pins. Output buffers are open drain CMOS . The device drives the output channels theoretically one bit time before they can be exploited as logical input channels (bit and slot compatibility is preserved): this feature allows inputs and outputs to be tied together cancelling any analog delay of digital outputs up to tDEL max = tbit - tPD(PCM)max + tPD(PCM)min MIXED RD and WR OPERATIONS In principle RD and WR operations are allowed in any order within specification constraints. In practive, only one control pin is low at any given time when CS1 and CS2 are enabled. If by mistake or hardware failure both RD and WR pins are low, the interface bus is internally pushed to tristate condition as long as WR is held low and input registers are protected. Registers OR1 and OR2 can be read in any order with a single RD strobe using C/D as multiplexing control ; never the less this procedure is not recommended because the device is directed for instruction flow only according to data latched by RD rising edge. Multiple RD operationsof the same kind are allowed without affecting the instruction flow : only "new" OR1 or OR2 read operations step the flow. Input and output registers are held for sure in the previous state for the first 3 cycles following an opcode or an OR2 read.
FUNCTIONAL DESCRIPTION OF SPECIFIC MICROPROCESSOR OPERATIONS The device, under microprocessor control, performs the following instructions : 1 CHANNEL CONNECTION 2 CHANNEL DISCONNECTION 3 LOADING OF A BYTE ON A PCM OUTPUT CHANNEL 4 TRANSFER OF A SINGLE PCM OUTPUT CHANNEL SAMPLE 5 TRANSFER OF A SINGLE OUTPUT CHANNEL CONTROL WORD 6 TRANSFER OF A SELECTED 0 CHANNEL PCM INPUT DATA ACCORDING TO AN 8-BIT MASK PREVIOUSLY STORED IN THE "EXPECTED MESSAGES" REGISTER The instruction flow is as follows. Any input protocol is started by the microprocessor interface loading the internal stack register with 2 bytes (4 bytes for instructions 1 and 3) qualified as data bytes by C/D = 0 and a specific opcode qualified by C/D = 1 (match condition is normally needed).
12/18
After the code is loaded in the instruction register it is immediately checked to see whether it is acceptable and if not it is rejected. If accepted the instruction is also processed as regards match condition and is appended for execution during the memories' spare cycles. Four cases are possible : a) the codeis not valid ; executioncannottake place, the DR output pin is reset to indicate the error ; all registers are saved ; b) the code is valid for types 2, 4 and 6 but it is unmatched ; execution cannot take place, DR is not affected. c) the code is valid for types 1 and 3 and it is unmatched ; the instruction is interpreted as a channel disconnection. d) the code is valid and is either matched or of type 5 ; the instruction is processed as received. Validation control takes only two cycles out of a total executiontime of 4 to 7 cycles ; the last operation is updating of the content of registers OR1 and OR2, according to the following instruction tables.
M3488
During a very long internal operation (device initialization after RESET going high or execution of instruction 6) a new set of data bytes with a valid opcode is accepted while a wrong code is rejected. At the end of the current routine execution takes place in the same way as described before. At the end of an instruction it is normally recommended to read one or both registers. To exploit instruction 6, however, it is mandatoryto read register OR2. This is because instruction 6, used between other short instructions of type 1 to 5, must have priority and can be enabled only after the short instructions have been completed. Instruction 6 normally has a long process and a special flow which is described below. First a not-all-zero mask is stored in the "expected messages" register and in another "background" register. This operation starts the second phase of instruction 6 which is called "channel 0 extraction" and is repeated at the beginning of any new time frame.At the beginningof the time frame a new copy of activated channels to be extracted is made from the "background register" and put in the "expected messages" register. In addition the latter register is modified to indicate the exact number of messages that have arrived. The term messages covers any input 0 channeldata with startingsequencedifferent from the label 01. So using this label the number of expected messages can be reduced to correspond to the number of effective messages. If and only if the residual number is different from zero will the device start the extraction protocol at the end of the current routine. The procedureis as follows : the DR outputis pulsed low as a two cycle interrupt request and OR2 is loaded with the total number of active channels to be extracted. The transfer of OR2 content to the microprocessor continues the extraction which consists of repeated steps of OR1 and OR2 loading, indicating respectively the message and the incoming bus number. Reading the registers in the order OR1, OR2 must be continued until completion or until the time frame runs out. With a new time frame a new extraction process begins, resuming the copy operation from the background register. During extraction the active channels are scanned from the highest to the lowest number (from 7 to 0). While extraction is being carried out the time interval requirements between active rising edges of RD are minimum 4 to 7 tCK for sequence OR2 - OR1 and minimum 2 times tCK for sequenceOR1 - OR2. More details are given in the following tables. INSTRUCTION TABLES The most significant digits of OR2 A7, A6, A5 are a copy of the PCM selected output bus ; the least significant digits of OR2 are the opcode, C8 is the control bit. In any case parentheses() define actual register content.
INSTRUCTION 1: CHANNEL CONNECTION
Control Signals Match C/D X X x X yes/no yes 0 0 0 0 1 0 CS 0 0 0 0 0 0 WR RD 0 0 0 0 0 1 1 1 1 1 1 0 D7 X X X X X D6 X X X X X D5 X X X X X C5 1 Bi0 Data Bus D4 X Ci4 X X C4 1 Ci4 C8 1 0 D3 X Ci3 X 0 C3 1 Ci3 0 0 0 D2 Bi2 Ci2 D1 Bi1 Ci1 D0 Bi0 Ci0
st
Notes 1 Data Byte: selected input bus. 2
nd
Data Byte: selected input channel.
Bo2 Bo1 Bo0 3 rd Data Byte: selected output bus. 0 C2 1 Ci2 0 0 0 0 1 Instruction Opcode
Co4 Co3 Co2 Co1 Co0 4th Data Byte: selected output channel. C1 C0 OR1: CM content copy, that is, 1 1) for mismatch condition, Ci1 Ci0) for match condition 0 0 0 1 1) 1) OR2: that is, for mismatch condition for match condition
C7 C6 (1 1 (Bi2 Bi1
yes
1
0
1
0
A7 A6 A5 (Bo2 Bo1 Bo0 (Bo2 Bo1 Bo0
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M3488
INSTRUCTION2: OUTPUT CHANNEL DISCONNECTION
Control Signals Match C/D CS X X Yes Yes Yes 0 0 1 0 1 0 0 0 0 0 WR 0 0 0 1 1 RD 1 1 1 0 0 D7 X X X 1 D6 X X X 1 D5 X X X 1 Data Bus D4 X X 1 1 1 D3 X 0 1 0 0 D2 D1 D0
st
Notes
Bo2 Bo1 Bo0 1 Data Byte: selected output bus. 0 1 1 1 1 1 1 1 0 1 1 1) Instruction Opcode OR1: CM Content Copy (output channel is inactive) OR2: that is.
Co4 Co3 Co2 Co1 Co0 2nd Data Byte: selected output channel.
A7 A6 A5 (Bo2 Bo1 Bo0
INSTRUCTION3: LOADING ON A PCM OUTPUT CHANNEL FROM A MICROPROCESSOR BYTE
Control Signals Match C/D CS WR X X X X Yes/no Yes Yes 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 RD 1 1 1 1 1 0 0 D7 X X X X X D6 X X X X X D5 X X X X X C5 1 Ci5 Data Bus D4 X Ci4 X X C4 1 Ci4 1 1 D3 X Ci3 X 0 C3 1 Ci3 0 0 D2 Ci7 Ci2 D1 Ci6 Ci1 D0
st
Notes 1 Data Byte: most significant digits to be inserted. 2 Data Byte: least significant digits to be inserted.
nd
Ci5 Ci0
Bo2 Bo1 Bo0 3rd Data Byte: selected output bus. 1 C2 1 Ci2 1 1 0 0 Instruction Opcode
Co4 Co3 Co2 Co1 Co0 4th Data Byte: selected output channel.. C1 C0 OR1: CM content copy, that is, 1 1) for mismatch condition, Ci1 Ci0) for match condition 1 1 1 1) OR2: that is.
C7 C6 (1 1 (Ci7 Ci6
A7 A6 A5 (Bo2 Bo1 Bo0
INSTRUCTION4: TRANSFER OF A SINGLE PCM SAMPLE
Control Signals Match C/D CS X X Yes Yes Yes 0 0 1 0 1 0 0 0 0 0 WR 0 0 0 1 1 RD 1 1 1 0 0 D7 X X X C7 S7 D6 X X X C6 S6 D5 X X X C5 S5 Data Bus D4 X X C4 S4 1 1 D3 X 1 C3 S3 0 0 D2 D1 D0
nd
Notes
Bo2 Bo1 Bo0 1st Data Byte: selected output bus. Data Byte: selected output channel. 0 C2 S2 1 1 1 C1 S1 1 1 1 C0 S0 1 1) Instruction Opcode OR1: CM Content Copy if C8 = 1; or SM Content Sample if C8 = 0 OR2: that is.
Co4 Co3 Co2 Co1 Co0 2
A7 A6 A5 (Bo2 Bo1 Bo0
Notes : S7...S0 is a parallel copy of a P CM data, S7 is the most significant digit and the first of the sequence.
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M3488
INSTRUCTION5: TRANSFER OF AN OUTPUT CHANNEL CONTROL WORD
Control Signals Match C/D CS X X Yes Yes Yes 0 0 1 0 1 0 0 0 0 0 WR 0 0 0 1 1 RD 1 1 1 0 0 D7 X X X C7 D6 X X X C6 D5 X X X C5 Data Bus D4 X X C4 D3 X 1 C3 1 1 D2 D1 D0
st
Notes
Bo2 Bo1 Bo0 1 Data Byte: selected output bus. 0 C2 0 0 0 C1 0 0 0 C0 0 0) Instruction Opcode OR1: CM selected CM word copy. OR2: that is.
Co4 Co3 Co2 Co1 Co0 2nd Data Byte: selected output channel.
A7 A6 A5 C8 (Bo2 Bo1 Bo0 C8
INSTRUCTION6: CHANNEL 0 SELECTION MASK STORE/DATA TRANSFER
Control Signals Match C/D CS X X Yes Yes Yes Yes Yes Yes Yes
No tes : 1. 2. 3. 4.
Data Bus RD 1 1 1 0 0 0 0 0 0 N2 S7 P2 N1 S6 P1 N2 N1 D7 X X X D6 X X X D5 X X X D4 X D3 X D2 D1 D0
WR 0 0 0 1 1 1 1 1 1
Notes 1st Data Byte: most sign. digits of selection mask. 2 Data Byte: least sign. digits of selection mask. Instruction Opcode OR1: register is not affected.
nd
0 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0 0
Mi7 Mi6 Mi5
Mi4 Mi3 Mi2 Mi1 Mi0 X 1 1 1 0
Mask store control (previous content) N0 Tn 1 1 1 0 OR2: see below. OR1: register is not affected. 1 S1 1 0 S0 0 OR2: see below. OR1: expected message stored in SM. OR2: see below.
First Data Transfer (after DR going low) (previous content) N0 S5 P0 Tn S4 Fn 1 S3 1 1 S2 1
Repeated Data Transfer (after first OR2 transfer)
About mask bits Mi0 to Mi7 a logic "0" level means disabling condition, a logic "1" level means enabling condition. A null mask or a RESET pulse clear the mask and the deep background mask registers and disable channel 0 extraction function. Reading of OR2 is optional after mask store or redefinition, because function is activated only by not-null mask writing. After mask store (N2 N1 N0) is the sum of activated channels, after DR is the sum of active channels ; Tn = 1/0 means activation/suppression of the function after store while after DR only Tn = 1 can appear to tell a not-null configuration to be extracted. 5. Reading of OR2 is imperative after DR in order to step the data transfer ; reading of OR1 is also needed to scan in descending order the priority register. Relevant messages only are considered, that means only messages with a MSD label different from 0 1. 6. (P2 P1 P0) is the PCM bus on which the message copied in OR1 was found ; Fn is a continuation bit telling respectively on level 1/0 for any more/no more extraction step to be performed.
M3488 WITH LESS PCM LINKS THAN 32 CHANNELS It is also possible to use M3488 when the PCM frames are made up of a number of channels other than 32. Suppose that the PCM frames are made up of NChannels, which will be numbered from 0 to (N-1). Each PCM frame will thus be made up of a number of bits multiplied by 8 ; this exactly equal to (N . 8). Also, in this case, it is necessary to respect the timing relationshipbetween the different signals shown on the data sheet ; in particular, a relation-ship is always carefully made between the rising edge of
SYNC and the first clock (CK) bit contained in the slot time for bit 0 of channel 0. In order to use M3488 with these frames, it is sufficient, using the data bytes sent by the microprocessor, to modify the numbering of a few channels. In particular : a) in all instructions in which reference is made to the input channel (N-1), the number 31 should be substituted for the number (N-1) ; b) in all instructions in which reference is made to the output channel 0, the number N should be substituted for the number 0.
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M3488
PQFP44 (10 x 10) PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B c D D1 D3 e E E1 E3 L L1 K 0.65 12.95 9.90 0.25 1.95 0.30 0.13 12.95 9.90 13.20 10.00 8.00 0.80 13.20 10.00 8.00 0.80 1.60 0(min.), 7(max.) 0.95 0.026 13.45 10.10 0.510 0.390 2.00 2.10 0.45 0.23 13.45 10.10 mm TYP. MAX. 2.45 0.010 0.077 0.012 0.005 0.51 0.390 0.52 0.394 0.315 0.031 0.520 0.394 0.315 0.031 0.063 0.037 0.530 0.398 0.079 0.083 0.018 0.009 0.53 0.398 MIN. inch TYP. MAX. 0.096
D D1 D3 A1
33 34 23 22
0.10mm .004 Seating Plane
A A2
E3
E1
B
44 1 11
12
E
B C L K
e L1
PQFP44
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M3488
DIP40 PACKAGE MECHANICAL DATA
DIM. MIN a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 48.26 14.1 0.175 0.130 0.23 1.27 52.58 16.68 0.598 0.100 1.900 0.555 mm TYP 0.63 0.45 0.31 0.009 0.050 2.070 0.657 MAX MIN inch TYP 0.025 0.018 0.012 MAX
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M3488
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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Price & Availability of M3488B1

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